The present invention relates to a multiplier, and specifically, is directed to a multiplier generally known as a serial/parallel multiplier.
FIG. 6 is a block diagram showing an arrangement of a conventional serial/parallel multiplier. FIG. 7 is an explanatory drawing showing a calculating operation performed by the conventional serial/parallel multiplier of FIG. 6. In the following explanation, multipliers K0 to K3 (K0 denotes an LSB, and K3 represents a sign bit) indicated by a 2's complement are multiplied by multiplicands D0 to D4 (D0 is an LSB, and D4 denotes a sign bit) indicated by a 2's complement.
First, a description will be made of each of the structural elements of the serial/parallel (serial-to-parallel) multiplier indicated in FIG. 6. AND gates 31a to 31c and a NAND gate 31d (referred to as logical product circuits where necessary) perform logical product operations for the multipliers K0 to K3 which are input in parallel into the serial/parallel multiplier, and for the multiplicands D0 to D4 which are sequentially input in series, for every 1 clock, to the multiplier. Full adders 32a to 32d add the outputs from the logical product circuits 31a to 31d, the outputs derived from the previous stage circuit, and the carry output, thereby outputting the added (summation) output to the next stage. Delay circuits 33a to 33d delay the carry outputs obtained from the full adders 32a to 32d by 1 clock time period in response to a clock signal BCK. Delay circuits 34d to 34b delay summation outputs from the full adders 32d to 32b by 1 clock time period, thereby supplying delayed summation outputs to the full adders 32c to 32a.
Referring now to FIG. 7, the operation of the serial/parallel multiplier shown in FIG. 6 will be explained. It should be noted that the following explanation is made based on the below-mentioned assumptions. It is now assumed that the multipliers K0 to K3 are not changed even when the multiplicands D0 to D4 are changed from present data to subsequent data. It is also assumed that the multiplicands D0 to D4 are continuously changed from present data to subsequent data, that is, when the multiplicands D0 to D4 are changed from the present data to the subsequent data, the data is input into the multiplier at intervals of one clock period. It should be understood that 3-bit expansion data bits D4 to D4 shown in FIG. 7 are identical to sign bits D4. In a serial/parallel multiplier, a correct calculation result can be obtained by employing the expansion data. Generally speaking, such expansion data is definitely required for the normal serial/parallel multiplier.
During a clock period in which the first multiplicand bit D0 of the present data is input to the multiplier, "K0D0", "K1D0", "K2D0" and "K3D0" (namely, inverted logic value of K3D0) are respectively output from the logical product circuits 31a to 31d. In the full adders 32a to 32d, a predetermined adding operation is carried out in response to these outputs from the AND circuits 31a to 31d and other signals.
Substantially the same operation as above is carried out also for the respective clock periods of the second multiplicand bit D1 and the third multiplicand bit D2 of the present data.
In a clock time period during which the fourth multiplicand bit D3 of the present data is input to the multiplier, first calculation data regarding the present data is newly output from the multiplier. In other words, the least significant bit (LSB) component of "(K3D0+1)+(K2D1)+(K1D2)+(K0D3)" is output from the full adder 32a as this first calculation data, and the upper digit bit components are added to the subsequent outputs (see FIG. 7).
A similar operation is carried out also in a clock time period during which the fifth multipli and bit D4 of the present data and the 3-bit expansion data bits D4 to D4 are input to the multiplier. The second to fifth calculation data of the present data are output from the full adder 12a.
The calculation (multiplication) results of the present data are obtained as described above. That is, the respective data within the present data output range shown in FIG. 7 are added to each other in the vertical direction in a similar manner to the normal adding calculation, thereby obtaining the calculation (multiplication) results of the present data.
When all of the clock time periods during which the expansion data D4 to D4 of the present data are entered into the multiplier are completed, a subsequent clock time period is commenced during which the first multiplicand bit d0 of the next data is input to the multiplier. At this time, (K3D4)+(K2D4)+(K1D4)+K0d0) are output from the full adder 12a (see FIG. 7). That is to say, data in which the present data and the subsequent data are mixed are output.
Also, in clock time periods during which the second multiplicand bit d1 and the third multiplicand bit d2 of the next data are input to the multiplier, data in which the present data and subsequent data are mixed are output. As a consequence, the data output from the full adder 32a during these three clock periods becomes invalid data as represented in FIG. 7, i.e. data which cannot be utilized as calculation (multiplication) results.
As previously stated, in the conventional serial-to-parallel multiplier there are time periods during which data are output in which the present data and the next data are mixed. The data during these time periods become invalid data, that is, such data cannot be used as calculation (multiplication) results. Therefore, the calculation time period including the time period for calculating such invalid data is prolonged, and it is difficult to carry out high-speed, high-precision multiplication.